汽車電子測試-虛擬化驗證
VIRTUAL VALIDATION

dSPACE VEOS Virtual ECU Software-in-the-Loop (SIL) Integration and Validation Solution

With the wave of Software-Defined Vehicles (SDV), the complexity and communication bandwidth of ECUs are growing explosively. Traditional validation methods relying on physical hardware-in-the-loop (HIL) test benches and real vehicle testing can no longer meet the rapid iterative software release cycles.

Jotactic brings you the dSPACE VEOS virtual validation solution. By simulating complex multi-ECU networks, restbus communication, and rich virtual I/O injection in a pure PC environment, it implements test front-loading, enabling fully functional closed-loop automated regression testing in the earliest stages of software development!

Core Mental Model: From Source Code to Virtual Proving Ground

The core concept of VEOS is to 'digital twin' the real vehicle environment to your standard PC. Whether it's Classic AUTOSAR, Adaptive AUTOSAR, or Linux/POSIX software stacks on heterogeneous microprocessors (SoC), they can be perfectly containerized and assembled into a vehicle-level offline virtual system.

Virtual Validation System Components (Three Core Containers)

  • check_circle V-ECU (Virtual ECU Container):A virtual controller (format is .vecu or FMI compliant .fmu) packaged by importing the software architecture (ARXML) from SystemDesk and combining it with TargetLink or application layer source code.
  • check_circle SIC (Simulation Interface Container):A vehicle dynamics or environmental behavior model container compiled and generated by Simulink paired with the Model Interface Package (MIP).
  • check_circle BSC (Bus Simulation Container):The restbus network and communication stack automatically generated by importing communication matrices such as DBC/LDF/ARXML from Bus Manager.

End-to-End Standard Workflow Quartet

VEOS virtual validation provides a highly standardized and deterministic four-step implementation process to ensure that the team's test assets can be 100% seamlessly reused in the subsequent HIL phase:

1

Modeling & Code Generation

Engineers design control algorithms in MATLAB/Simulink, or use SystemDesk to define AUTOSAR software components and architectures, combine application layer code with BSW (Basic Software) specifications, and compile and package them into .vecu, .sic, or standard FMU containers.

2

Bus Configuration and Restbus Simulation

Use dSPACE Bus Manager to import the communication matrix provided by the automaker, configure gateway routing, signals, and signal groups, and construct virtual CAN, LIN, and Automotive Ethernet topologies.

3

System Integration Build

In the VEOS main editor, import multiple decoupled containers such as V-ECU, SIC, and BSC. Use the intuitive Port Topology interface for signal connection and network alignment, and finally build it into an independent offline simulation application file (.osa) with one click, while automatically generating SDF and TRC files for observing variables.

VECU 系統整合
4

Experiment Operation and Automated Testing (Experiment & Test Automation)

Load the generated .osa into ControlDesk and manually design an intuitive HMI dashboard to observe signals; or combine with AutomationDesk / Python (RTT SDK) to write standard ASAM XIL API test scripts, automatically execute stimulus (Signal Editor) and assertion verification, and record standard MF4 data.

TECHNOLOGY HIGHLIGHTS

Four Major Technical Highlights

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Highlight 1: Heterogeneous Multi-Core and Cross-Platform Virtual Communication Networks

Modern in-vehicle local area networks (LANs) contain various different operating systems and underlying communication architectures. VEOS supports the simultaneous scheduling and execution of heterogeneous controllers within a single virtual environment and provides extremely precise time synchronization.

  • 🚗 Classic and Adaptive V-ECUs Dancing on the Same Stage:Simulate the dynamic interaction between multi-core MCUs (running Classic AUTOSAR on microcontroller OS) and high-computing SoCs (running Adaptive AUTOSAR or ROS 2 software stacks based on POSIX / Linux).
  • 🌐 Virtual Ethernet & SOME/IP:In a pure PC virtual network card environment, accurately simulate the discovery (Service Discovery), subscription, and object serialized transmission of SOME/IP services, effortlessly reproducing the complex dynamics of automotive Ethernet.
  • ⏱️ Global Time Synchronization:VEOS features a highly optimized Virtual Simulation Time manager. Regardless of the computational complexity, all heterogeneous containers (V-ECU, environmental models, restbus) have their time steps uniformly advanced by the VEOS core, ensuring that data exchange maintains complete determinism at the microsecond timing level, completely eliminating occasional timing jitter and data desynchronization.
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Highlight 2: Powerful Co-Simulation and Third-Party Collaborative Expansion

To achieve perfect closed-loop testing, VEOS provides an extremely open Co-Simulation architecture:

  • check FMI / FMU Industry Standards:Fully supports the Functional Mock-up Interface specification. Whether it is a CarSim vehicle dynamics model, an Amesim electrical subsystem, or a third-party self-developed model, it can be seamlessly imported into VEOS integration in a black-box manner.
  • check Data Replay and Hardware Coupling (JSON Client):Supports external real-time streaming via JSON protocol and Co-Simulation Client (CoSim Client). Can be used to import data replay (Log Replay) of real road test records, or link the virtual controller on the PC with external real hardware boards and sensor simulators.
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Highlight 3: Multi-Dimensional Virtual I/O Injection and Fault Simulation

In the SIL phase without real hardware wiring, VEOS provides innovative 'Virtual I/O Injection' technology, allowing engineers to freely operate and intervene in the underlying Microcontroller Abstraction Layer (MCAL) of the tested V-ECU:

🔌Stimulus and Error Simulation Types
  • check Low-level Register Value Intervention:Directly inject virtual ADC sampling voltages, PWM duty cycles, or GPIO high/low state.
  • check Virtual Fault Injection:Simulate sensor line open circuits, short circuits to ground, signal stuck, or communication packet loss at the software layer, perfectly testing the diagnostic trouble code (DTC) generation logic and fail-safe degradation strategies of the V-ECU, meeting the strict requirements of ISO 26262 functional safety.
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Highlight 4: Python Automated Testing and CI/CD Pipeline Compliant with ASAM XIL Standards

VEOS is the ultimate tool for large project teams to implement DevSecOps and Continuous Integration (CI/CD):

  • check ASAM XIL MAPort Standardized Access:The test scripts are fully compliant with the ASAM XIL standard, and whether the underlying layer is a virtual environment (VEOS) or a physical cabinet (SCALEXIO), the same API interface is used to read and write model variables.
  • check Python Real-Time Testing (RTT SDK):Combined with Pytest or Robot Framework, the test code can be synchronously advanced with the simulation core at the millisecond level.
  • check Docker Containerized Cloud Large-Scale Parallelism:VEOS and OSA applications can be perfectly packaged into Docker images and deployed in enterprise-level automated pipelines such as Jenkins. When new code is submitted, thousands of test cases can be triggered in parallel on cloud servers to achieve comprehensive automated regression.

Three Core Engineering Benefits of Adopting VEOS

🚀

Accelerate Time-to-Market

No need to wait for chip arrival or HIL cabinet scheduling; full system closed-loop testing can be initiated during the architecture design phase of the V-model, shortening the project cycle by more than 30%.

📉

Drastically Reduce Error Correction Costs

According to statistics, 80% of application layer and communication logic errors can be detected in the VEOS SIL phase on the pure PC side, preventing errors from flowing into the HIL or real vehicle phases and causing high rework costs.

🔄

100% Perfect Reuse of Test Assets

The models built in VEOS, communication BSCs, ControlDesk layout panels, and automated test scripts are 100% seamlessly and losslessly reused in the HIL phase, maximizing the value of the enterprise's engineering R&D assets.